PLL chip cuts jitter for optical transport networks

Silicon Laboratories has introduced a multi-channel clock ICs for high-speed optical transport networks (OTNs).

Using the firm's digital phase-locked loop (PLL) technology (see below), the Si5374 and Si5375 clocks are said to "providing twice the PLL integration and 40% lower jitter than competing solutions",

OTN is a next-generation protocol (ITU G.8251 and G.709) that multiplexes different services onto optical networks, making it a suitable solution for edge routers, wavelength division multiplexing (WDM) transmission equipment, carrier Ethernet and multi-service platforms.

"OTN applications pose complex timing challenges by requiring multiple low-jitter clocks at non-integer-related frequencies," said the firm. "The Si537x devices produce up to eight low-jitter output clocks, simplifying the design of any-protocol, any-port 10G, 40G and 100G OTN line cards."

claimed Silicon Labs.

Each clock multiplier can be configured to generate any frequency from 2kHz-808MHz from a 2kHz-710MHz input.

"Jitter performance of 0.4ps eliminates the need for discrete VCXO-based PLLs currently used in OTU3 and OTU4 applications," claimed the firm. and the devices can reliably lock to gapped clock inputs - a critical OTN line card clock requirement - without separate upstream low-bandwidth PLLs."

Other carrier-grade features include SONET-compatible jitter peaking (0.1dB max) and circuitry to minimise output clock phase transients during reference switching.

"Each PLL engine features an integrated loop filter that supports user-programmable bandwidths as low as 4 Hz, enabling wander filtering in addition to jitter attenuation, configurable on a per channel basis," said Silicon Labs. Si5374 device has eight input clocks and eight output clocks enabling a design to support SONET/SDH, 1/10/100G Ethernet, 1/2/4/8/10G Fibre Channel and 3G/HD SDI video simultaneously, while Si5375 has four input clocks and four output clocks.

The firm considers the chips an upgrade from its existing Si5319/26 jitter-attenuating clocks, offering a more integrated jitter-cleaning clock solution. "Si537x clocks effectively replace four timing devices with a single IC in high-port-count 10G/40G/100G OTN line cards."

Silicon Labs' DSP-enhanced PLL technology is claimed to "eliminate numerous complex manufacturing steps required to frequency tune traditional SAW and crystal-based implementations by moving the frequency synthesis capability into a mixed-signal IC. The use of a low-frequency crystal provides improvements in aging, temperature stability and mechanical reliability".