ARM aims to speed up multicore chip debug

ARM has launched CoreSight SoC-400, which is a configurable debug and trace tree for multicore SoC designs.

“Until recently debug and trace solutions have been an afterthought in the SoC design process, as basic functionality was acceptable in less demanding applications,” said Mike Dimelow, marketing director, processor division, ARM.

“However, as multicore applications are more common-place, debug and trace solutions become critical to SoC designers and software developers,” said Dimelow. 

CoreSight SoC-400 is based on the ARM CoreSight debug and trace architecture which is used for hardware and software design.

But it extends the CoreSight architecture from existing debug and trace design kits for specific IP, such as ARM Cortex-A9 and ARM Cortex-R4 processors, into a system level solution that provides configurable components and buses which are modular and completely scalable.

“The demand for complex applications development on multicore SoCs, such as TI’s OMAP4 platform, continues to increase. ARM's CoreSight can provide advanced debug and trace solutions to aid developers on these platforms," said Stephen Lau, product manager, debug technology, wireless business unit, TI.

Another benefit for debug and trace infrastructure is the inclusion of the CoreLink AMBA Designer tool.

CoreSight SoC-400 features automated system stitching and test benches and enhanced AMBA AXI Access Port (AXI-AP) functionality, supporting 64 bit address space across the AXI bus.

Local and global time stamping is also possible. All components of the CoreSight SoC-400 are supplied with IPXACT descriptors for use with AMBA Designer.