IMEC and Atrenta demo stacked die design flow

Belgian lab IMEC and Californian EDA firm Atrenta have developed a planning and partitioning design flow for heterogeneous 3D stacked ICs.

Packages containing more than one die in a stack are being developed to reduce footprint and connection length.

"To design applications with 3D stacked dies, the ability to do early planning and partitioning is critical. The number of potential solutions for any given system design problem is very large," said IMEC. "For example: front-to-front or front-to-back stacking, silicon interposer, via configurations and partitioning. Exploring this solution space through multiple full designs is simply too expensive and time-consuming."

The tool allows partitioning and prototyping early in the design process, before detailed implementation begins.

Heat and mechanical stress are other issues that need exploration.

IMEC has been working on 3D stacked assemblies for years and has developed thermal and mechanical models that generate heat dissipation and mechanical stress maps, and has validated them using packaged stacked DRAM-on-logic die.

"When combining the design floor plans produced by Atrenta's SpyGlass physical 3D prototyping tool with the stress models developed by IMEC, different scenarios can be assessed and the best option can be chosen in advance of a full design implementation," claimed IMEC.

Potential applications include: ICs for mobile devices, high-speed electronics, imagers, stacked DRAM, and solid-state drives.

The flow will be demonstrated at the Design Automation Conference (DAC) in San Diego (June 6-8).

It will include design partitioning across a 3D stack with routing congestion analysis, through-silicon via placement, back-side re-distribution layer routing, and thermal profile display on the 3D floor plan.